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FUJITSU SEMICONDUCTOR Data Sheet (Advance Information)
Advance Information
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90495 Series
MB90497/F497
1. OUTLINE
The MB90495-series with FULL-CAN interface and FLASH ROM is especially designed for automotive and industrial applications. Its main feature is the on-chip CAN Interface, which conforms to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme, including 8 message buffers, and so offering more functions than a normal full CAN approach. With the new 0.5 mm CMOS technology, Fujitsu now also offers on-chip FLASH-ROM program memory. An internal voltage booster removes the necessity for a second programming voltage. An on-chip voltage regulator provides 3V to the internal MCU core. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 62.5 nsec instruction cycle time from an external 4 MHz clock. A 32kHz Subsystem clock has been included for power saving modes and real time measurement. There are 2 on-chip UART's, which also provide synchronous communication modes. Furthermore the MCU features an 8 channel ADC, 8 channel External interrupt controller, two 16 bit PPG channels, 4 channel Input Capture Unit and a 16-bit free running I/O-timer.
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2. FEATURES
* * * * * * * * * * * * * * 16-bit core CPU; 4MHz external clock (16 MHz internal, 62.5 ns instruction cycle time) 32kHz Subsystem Clock 0.5 mm CMOS Technology Internal voltage regulator supports 3V MCU core, offering low EMI and low power consumption figures 64 KB FLASH ROM; supports automatic programming, 10.000 erase cycles, 10 year data retention time and no second programming voltage required 2 KB static RAM FULL-CAN interface; conforming to Version 2.0 Part A and Part B, flexible message buffering (mailbox and FIFO buffering can be mixed) 2 UART's; both offering synchronous communication modes. Powerful interrupt functions (8 programmable priority levels; 8 external interrupts) I/O Timer A/D Converter: 8 channel analogue inputs (Resolution 10 bits or 8 bits) ICU (Input capture) 16bit * 4ch PPG (Programmable Pulse Generator) 16bit * 2ch; Can be configured as 8bit * 4ch Optimised instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) 4-byte instruction execution queue Signed multiply (16bit*16bit) and divide (32bit/16bit) instructions available Program Patch Function Fast Interrupt processing 16-bit reload timer: 2 channels Low Power Consumption - Several different Lo-Power modes: (Sleep, Stop, Watch,...) Package: QFP-64; 12mm x 12mm body, 0.65mm pin pitch QFP-64; 20mm x 18mm body, 1.0mm pin pitch
* * * * * * * *
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3. PRODUCT LINEUP
The following table provides an overview of the MB90495 Series
Features
CPU System clock
MB90F497
F2MC-16LX CPU
On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stop) Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x4) Boot-block Flash memory 64 Kbytes 2 Kbytes 0.5 mm CMOS with on-chip voltage regulator for internal power supply + Flash memory Onchip charge pump for programming voltage
MB90497
ROM RAM
Mask ROM 64 Kbytes 2 Kbytes 0.5 mm CMOS with on-chip voltage regulator for internal power supply
Technology
Operating voltage range Temperature range Package
5 V +/- 10% - 40 to 85 C QFP64
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4. BLOCK DIAGRAM
X0,X1 RSTX X0A, X1A
Clock Controller Watch Timer Time Base Timer RAM 2K ROM/Flash 64K
Prescaler
16LX CPU
IO Timer Input Capture 4ch 16-bit PPG 2ch
FRCK
IN[3:0]
PPG[3:0]
Prescaler
FMC-16 Bus
SOT1 SCK1 SIN1
UART 1 (SCI)
CAN
RX TX
SOT 0 SCK0 SIN0
AVCC AVSS AN[7:0] AVR ADTG
External Interrupt
INT[7:0]
UART 0 (SCI)
16bit Reload Timer 2ch 10-bit ADC 8ch
TIN[1:0] TOT[1:0]
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5. PIN ASSIGNMENT
P43/TX
VSS P30/ALE/SOUT0 P31/RDX/SCK0 P32/WRLX/SIN0 P33/WRHX P34/HRQ P35/HAKX VCC C P36/FRCK/RDY P37/ADTG/CLK P40/SIN1 P41/SCK1 P42/SOUT1
P44/RX
P31/RDX/SCK0 P32/WRLX/SIN0 P33/WRHX P34/HRQ P35/HAKX VCC C P36/FRCK/RDY P37/ADTG/CLK P40/SIN1 P41/SCK1 P42/SOUT1
P43/TX
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
52 53 54 55 56 57 58 59 60 61 62 63 64
MB90495 Series Data Sheet (Advance Information)
51 50 49 48 48 P27/INT7/A23 P26/INT6/A22
P44/RX
QFP-64
QFP-64
Figure 5.2 FPT-64P-M06 Package code (mold) FPT-64P-M09
P61/INT1 P62/INT2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 X0A X1A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/ALE/SOUT0 VSS P27/INT7/A23 P26/INT6/A22 P25/INT5/A21 P24/INT4/A20 P23/TOUT1/A19 P22/TIN1/A18 P21/TOUT0/A17 P20/TIN0/A16 P17/PPG3/AD15 P16/PPG2/AD14 P15/PPG1/AD13 P14/PPG0/AD12 P13/IN3/AD11 P12//IN2/AD10 P11/IN1/AD09 P10/IN0/AD08 P07/AD07
Figure 5.1 FPT-64P-M09
Package code (mold) FPT-64P-M06
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P61/INT1 P62/INT2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 X0A X1A
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P25/INT5/A21 P24/INT4/A20 P23/TOUT1/A19 P22/TIN1/A18 P21/TOUT0/A17 P20/TIN0/A16 P17/PPG3/AD15 P16/PPG2/AD14 P15/PPG1/AD13 P14/PPG0/AD12 P13/IN3/AD11 P12//IN2/AD10 P11/IN1/AD09 P10/IN0/AD08
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P63/INT3 MD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
P06/AD06
P07/AD07
P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VSS X1 X0 MD2 MD1 RSTX MD0 P63/INT3
32 31 30 29 28 27 26 25 24 23 22 21 20
P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VSS X1 X0 MD2 MD1 RSTX
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6. PIN DESCRIPTION
6.1 Pin Function
Pin No. Pin Name M06 2 3 4 to 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 M09 1 2 3 to 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P61 INT1 P62 INT2 P50 to P57 AN0 to AN7 AVCC AVR AVSS P60 INT0 X0A X1A P63 INT3 MD0 RSTX MD1 MD2 X0 X1 VSS G H CMOS/ TTL CMOS/ TTL High-Z Port D A A D C B C F A A H H L H H CMOS/ TTL CMOS CMOS CMOS CMOS High-Z Port H CMOS/ TTL High-Z Port Circuit Type D D E Active Level CMOS/ TTL CMOS/ TTL CMOS at RST Priority Function General pupose IO External Interrupt input 1 General pupose IO External interrupt 2 General pupose IO Inputs for A/D Converter Dedicated power supply for A/D Converter Reference Volgate inupt for A/D Converter Dedicated power ground for A/D Converter General pupose IO External interrupt input 0 Low frequency oscillation input Low frequency oscillation output General purpose IO External interrupt 3 Mode input Reset input Mode input Mode input High frequency oscillation input High frequency oscillation output Power ground General purpose IO Addresss Data Bus General pupose IO Inputs for Input Captures Address Data Bus General pupose IO Outputs for Programable Pulse Generators Address Data Bus General pupose IO Input for 16-bit Reload Timer 0 Address Bus General pupose IO Output for 16-bit Reload Timer 0 Address Bus General pupose IO Input for 16-bit Reload Timer 1 Address Bus
H H H
High-Z High-Z High-Z
Port Port Port
26 to 33 25 to 32
P00 to P07 AD00 to AD07 P10 to P13 34 to 37 33 to 36 IN0 to IN3 AD08 to AD11 P14 to P17 38 to 41 37 to 40 PPG0 to PPG3 AD12 to AD15 P20 TIN0 A16 P21 TOT0 A17 P22 TIN1 A18
G
H
High-Z
Port
G
H
CMOS/ TTL
High-Z
Port
42
41
G
H
CMOS/ TTL CMOS/ TTL CMOS/ TTL
High-Z
Port
43
42
G
H
High-Z
Port
44
43
G
H
High-Z
Port
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Pin No. Pin Name M06 45 M09 44 P23 TOT1 A19 P24 to P25 INT4 to INT 7 A20 to A23 VSS P30 SOT0 ALE P31 SCK0 RDX P32 SIN0 WRLX P33 WRHX P34 HRQ P35 HAKX VCC C P36 FRCK RDY P37 ADTG CLK P40 SIN1 P41 SCK1 P42 SOT1 P43 Tx P44 Rx CMOS/ TTL G H CMOS/ TTL CMOS/ TTL CMOS/ TTL CMOS/ TTL CMOS/ TTL CMOS/ TTL High-Z Port Circuit Type
Active
Level
at RST
Priority
Function General pupose IO Output for 16-bit Reload Timer 1 Address Bus General pupose IO Inputs for External Interrupt Address Bus Ground General pupose IO Output for UART 0 Address Latch Enable output General pupose IO Input/Output for UART 0 Read Enable output General pupose IO Input for UART 0 Write Enable Low-byte output General pupose IO Write Enable High-byte output General pupose IO Halt Request input General pupose IO Halt Acknowledge output Power supply Pin for capacitor for the internal power supply. General pupose IO Inupt for IO Timer Ready input General pupose IO Trigger inupt for A/D Converter Clock output General pupose IO Input for UART 1 General pupose IO Input/Output for UART 1 General pupose IO Output for UART 1 General pupose IO CAN Transmit pin General pupose IO CAN receive pin
G
H
CMOS/ TTL CMOS/ TTL
High-Z
Port
46 to 49 45 to 48 50 51 49 50
G
H
High-Z
Port
52
51
G
H
High-Z
Port
53
52
G
H
High-Z
Port
54 55 56 57 58
53 54 55 56 57
G G G
H H H
High-Z High-Z High-Z
Port Port Port
59
58
G
H
High-Z
Port
60
59
D
H
CMOS CMOS/ TTL CMOS/ TTL CMOS/ TTL CMOS/ TTL CMOS/ TTL
High-Z
Port
61 62 63 64 1
60 61 62 63 64
G G G G G
H H H H H
High-Z High-Z High-Z High-Z High-Z
Port Port Port Port Port
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6.2 I/O Circuit Types
Circuit
X1 X1A
Drawing
Comment
1 0 1 0 1 0 11 00
11 00
Standby Control Signal
A
X0 X0A
B
11 00 11 00
C
1 0 1 0 1 0 1 0 111 000 11 00 1 0
HYS
HYS
D
HYS
1 0 1111 0000
Standby Control Signal
E
1 0 11 00 11 00
F
111 000
HYS
1 0 1 0 1 0
HYS
Standby Control Signal Analog
1 0 1 0
G
1 0
111 000 11 00 11 00
1 0 1 0 1 0
HYS Standby Control Signal TTL
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7. HANDLING DEVICES
(1) Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions: A voltage higher than Vcc or lower than Vss is applied to an input or output pin. A voltage higher than the rated voltage is applied between Vcc and Vss. The AVcc power supply is applied before the Vcc voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device.
(2) Handling unused input pins
Do not leave unused input pins open, as doing so may cause misoperation of the device. Use a pull-up or pull-down resistor.
(3) Using external clock
To use external clock, drive the X0 and X1 pins in reverse phase. Below is a diagram of how to use external clock.
MB90495 Series X0 X1
Figure 7.1 Using external clock
(4) Power supply pins (Vcc/Vss)
Ensure that all Vcc-level power supply pins are at the same potential. In addition, ensure the same for all Vss-level power supply pins. (See the figure below.) If there are more than one Vcc or Vss system, the device may operate incorrectly even within the guaranteed operating range. Note that this product may not have as many power pins as pictured in the figure.
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Vcc Vss
Vcc Vss Vcc
Vss
MB90495 Series
Vcc Vss
Vss
Vcc
Figure 7.2 Power pin connections
(5) Pull-up/down resistors
The MB90495 Series does not support internal pull-up/down resistors. Use external components where needed.
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8. ADDRESS SPACE MB90V495 FFFFFFH
ROM FF FLASH ROM FF ROM FF
MB90F497
MB90497
FF0000H FEFFFFH
ROM FE No Acess
FE0000H FDFFFFH
ROM FD
FD0000H FCFFFFH
ROM FC
FC0000H FBFFFFH
ROM FB
External bus access
External bus access
FB0000H FAFFFFH
ROM FA
FA0000H 010000H 00FFFFH
FF ROM mirror FF ROM mirror FF ROM mirror
004000H 003FFFH 003800H
Extended I/O
Extended I/O
Extended I/O
External bus access
External bus access
0018FFH 0010FFH 000900H 0008FFH 000100H 0000BFH 000000H
I/O RAM
RAM mirror1 Do not use
RAM mirror Do not use.
RAM
RAM
I/O
I/O
1. The RAM contents of 0000H - 08FFH is mirrored to 0900H - 10FFH. The RAM mirror area should not be accessed for proper operation.
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9. REGISTER MAP
Address 00 H 01 H 02 H 03 H 04 H 05 H 06 H 07-0F H 10 H 11 H 12 H 13 H 14 H 15 H 16 H 17-1A H 1B H 1C - 1F H 20 H 21 H 22 H 23 H 24 H 25 H 26 H 27 H 28 H 29 H 2A H 2B H 2C - 2F H 30 H 31 H 32 H 33 H 34 H 34 H 36 H 37 H 38-3FH 40 H 41 H 42 H PPG0 operation mode control register PPG1 operation mode control register PPG0 and PPG1 clock select register External Interrupt Enable External Interrupt Request External Interrupt Level External Interrupt Level A/D Control Status 0 A/D Control Status 1 A/D Data 0 A/D Data 1 UART 1 Prescaler Control Register Serial Mode Register 1 Serial Control Register 1 Input/Output Data Register 1 Serial Status Register 1 UART 0 Prescaler Control Register UART 0 edge select Serial Mode Control Register 1 Serial Control Register Input/Output Data Register 1 Serial Status Register 1 Analog Input Enable Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 Reserved DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 Reserved ADER Reserved SMR0 SCR0 SIDR0/SODR0 SSR0 CDCR0 SES0 SMC1 SRC1 SIDR1/SODR1 SMC1 Reserved CDCR0 Reserved ENIR EIRR ELVR ELVR ADCS0 ADCS1 ADCR0 ADCR1 Reserved PPGC0 PPGC1 PPG01 16-bit Programable Pulse Generator 0/1 R/W R/W R/W 0_00X__1 0_00X001 000000__ A/D Converter External Interrupt R/W R/W R/W R/W R/W R/W R R/W 00000000 XXXXXXXX 00000000 00000000 00000000 00000100 XXXXXXXX 00000_XX Prescaler UART 1 R/W 0___0000 UART1 UART0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000 00000100 XXXXXXXX 00001_00 0___1111 _______1 00XXXX00 00000X00 XXXXXXXX XXXXX000 Port 5, A/D R/W 11111111 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 R/W R/W R/W R/W R/W R/W R/W 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Peripheral Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Access Initial value R/W R/W R/W R/W R/W R/W R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
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Address 43 H 44 H 45 H 46 H 47-4FH 50 H 51 H 52 H 53 H 54 H 55 H 56 H 57 H 58 H 59 H 5A H 5B H 5C H 5D H 5E - 65 H 66 H 67 H 68 H 69 H 6A - 6E H 6F H 70-7F H 80-8F H 90-9D H 9E H 9F H A0 H A1 H A2-A4 H A5 H A6 H A7 H A8 H A9 H AA-AD H AE H AF H Flash Control Status (Flash only, otherwise reserved) Automatic ready function select reg. External address output control reg. Bus control signal select register Watchdog Control Time Base Timer Control ROM Correction Control Status Delayed Interrupt/release Low-power Mode Clock Selector ROM Mirror Timer Control Status 0 Timer Control Status 0 Timer Control Status 1 Timer Control Status 1 Input Capture 0 Input Capture 0 Input Capture 1 Input Capture 1 Input Capture Control Status 0/1 Input Capture Control Status 2/3 Timer Data Timer Data Timer Control Timer Control Input Capture 2 Input Capture 2 Input Capture 3 Input Capture 3 PPG2 operation mode control register PPG3 operation mode control register PPG2 and PPG3 clock select register Register Abbreviation Reserved PPGC2 PPGC3 PPG23 Reserved IPCP0 IPCP0 IPCP1 IPCP1 ICS01 ICS23 TCDT TCDT TCCS TCCS IPCP2 IPCP2 IPCP3 IPCP3 Reserved TMCSR0 TMCSR0 TMCSR1 TMCSR1 Reserved ROMM Reserved Reserved for CAN 1 Interface . Refer to "CAN Controller" Reserved PACSR DIRR LPMCR CKSCR Reserved ARSR HACR ECSR WDTC TBTC Reserved FMCS Reserved Flash Memory R/W 000X0000 W W W Watchdog Timer Time Base Timer External Memory Access R/W R/W 0011__00 00000000 0000000_ XXXXX111 1__0X100 ROM Correction Delayed Interrupt Low Power Controller Low Power Controller R/W R/W R/W R/W 11000000 _______0 00011000 11111100 ROM Mirror R/W 000____1 16-bit Reload Timer 0 R/W R/W R/W R/W 00000X00 ____0000 00000X00 ____0000 Input Captue 2/3 I/O Timer Input Capture 0/1/2/3 Input Captue 0/1 R R R R R/W R/W R/W R/W R/W R/W R R R R XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XX000000 XX000000 00000000 00000000 00000000 0__00000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator 2/3 R/W R/W R/W 0_00X__1 0_00X001 000000__ Peripheral Access Initial value
16-bit Reload Timer 1
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Address B0 H B1 H B2 H B3 H B4 H B5 H B6 H B7 H B8 H B9 H BA H BB H BC H BD H BE H BF H CO-FF H 1FF0H1FF5H 3900 H 3901 H 3902 H 3903 H 3904-390FH 3910 H 3911 H 3912 H 3913 H 3914 H 3915 H 3916 H 3917 H 3918-392FH 3930-3BFFH 3C003CFFH 3D003DFFH 3E00-3EFFH 3FF0-3FFFH
Register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15
Abbreviation ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Reserved ROM correction
Peripheral
Access Initial value R/W R/W R/W R/W R/W R/W R/W 11000111 11000111 11000111 11000111 11000111 11000111 11000111 11000111 11000111 11000111 11000111 11000111 11000111 11000111 11000111 11000111
Interrupt controller
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Timer 0/Reload 0 Timer 0/Reload 0 Timer 1/Reload 1 Timer 1/Reload 1
TMR0/TMRL0 TMR0/TMRL0 TMR1/TMRL1 TMR1/TMRL1 Reserved
16-bit Reload Timer 0
R/W R/W R/W R/W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
16-bit Reload Timer 1
PPG0 Reload L PPG0 Reload H PPG1 Reload L PPG1 Reload H PPG2 Reload L PPG2 Reload H PPG3 Reload L PPG3 Reload H
PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 Reserved Reserved 16-bit Programable Pulse Generator 2/3 16-bit Programable Pulse Generator 0/1
R/W R/W R/W R/W R/W R/W R/W R/W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved for CAN 1 Interface. Refer to "CAN Controller" Reserved for CAN 1 Interface. Refer to "CAN Controller" Reserved Reserved
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10. CAN CONTROLLER
The CAN controller has the following features: * Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats * * Supports transmitting of data frames by receiving remote frames 8 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration * Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1D acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats * Bit rate programmable from 10 Kbits/s to 2 Mbits/s (when input clock is at 16 MHz)
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10.1 List of Control Registers
Address 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 003D00H 003D01H 003D02H 003D03H 003D04H 003D05H 003D06H 003D07H 003D08H 003D09H 003D0AH 003D0BH 003D0CH 003D0DH 003D0EH 003D0FH 003D10H 003D11H 003D12H 003D13H 003D14H 003D15H 003D16H 003D17H 003D18H 003D19H 003D1AH 003D1BH Acceptance mask register 1 AMR1 R/W XXXXX--- XXXXXXXX Acceptance mask register 0 AMR0 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX Register Message buffer valid register Unused Transmit request register Unused Transmit cancel register Unused Transmit complete register Unused Receive complete register Unused Remote request receiving register Unused Receive overrun register Unused Receive interrupt enable register Unused Control status register Last event indicator register Receive/transmit error counter Bit timing register IDE register Unused Transmit RTR register Unused Remote frame receive waiting register Unused Transmit interrupt enable register Unused Acceptance mask select register Unused XXXXXXXX XXXXXXXX AMSR R/W XXXXXXXX XXXXXXXX TIER R/W 00000000 RFWTR R/W XXXXXXXX TRTRR R/W 00000000 CSR LEIR RTEC BTR IDER R/W, R R/W R R/W R/W 00---000 0----0-1 -------- 000-0000 00000000 00000000 -1111111 11111111 XXXXXXXX RIER R/W 00000000 ROVRR R/W 00000000 RRTRR R/W 00000000 RCR R/W 00000000 TCR R/W 00000000 TCANR W 00000000 TREQR R/W 00000000 Abbreviation BVALR Access R/W Initial Value 00000000
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10.2 List of Message Buffers (ID Registers)
Address 003C00H to 003C0FH 003C10H 003C11H 003C12H 003C13H 003C14H 003C15H 003C16H 003C17H 003C18H 003C19H 003C1AH 003C1BH 003C1CH 003C1DH 003C1EH 003C1FH 003C20H 003C21H 003C22H 003C23H 003C24H 003C25H 003C26H 003C27H 003C28H 003C29H 003C2AH 003C2BH 003C2CH 003C2DH 003C2EH 003C2FH ID register 7 IDR7 R/W XXXXX--- XXXXXXXX ID register 6 IDR6 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 5 IDR5 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 4 IDR4 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 3 IDR3 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 2 IDR2 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 1 IDR1 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 0 IDR0 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX Register General-purpose RAM Abbreviation -Access R/W Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX XXXXXXXX
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10.3 List of Message Buffers (DLC Registers and Data Registers)
Address 003C30H 003C31H 003C32H 003C33H 003C34H 003C35H 003C36H 003C37H 003C38H 003C39H 003C3AH 003C3BH 003C3CH 003C3DH 003C3EH 003C3FH 003C40H to 003C47H 003C48H to 003C4FH 003C50H to 003C57H 003C58H to 003C5FH 003C60H to 003C67H 003C68H to 003C6FH 003C70H to 003C77H 003C78H to 003C7FH Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 Data register 0 (8 bytes) Data register 1 (8 bytes) Data register 2 (8 bytes) Data register 3 (8 bytes) Data register 4 (8 bytes) Data register 5 (8 bytes) Data register 6 (8 bytes) Data register 7 (8 bytes) Abbreviation DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 Access R/W R/W R/W R/W R/W R/W R/W R/W Initial Value ----XXXX ----XXXX ----XXXX ----XXXX ----XXXX ----XXXX ----XXXX ----XXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX
DTR0
R/W
DTR1
R/W
DTR2
R/W
DTR3
R/W
DTR4
R/W
DTR5
R/W
DTR6
R/W
DTR7
R/W
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11. INTERRUPTS
Interrupt vector Interrupt cause Reset INT9 instruction Exception CAN RX CAN TX/NS Reserved Reserved External Interrupt INT0/INT1 Time Base Timer 16-bit Reload Timer 0 A/D Converter I/O Timer External Interrupt INT2/INT3 Reserved PPG 0/1 Input Capture 0 External Interrupt INT4/INT5 Input Capture 1 PPG 2/3 External Interrupt INT6/INT7 Watch Timer Reserved Input Capture 2/3 Reserved Reserved Reserved Reserved Reserved 16-bit Reload Timer 1 UART 0 RX UART 0 TX UART 1 RX UART 1 TX Flash Memory Delayed interrupt DMA Ch. Number ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- # 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15 # 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27 # 28 # 29 # 30 # 31 # 32 # 33 # 34 # 35 # 36 # 37 # 38 # 39 # 40 # 41 # 42 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Number ---- ---- ---- ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Address ---- ---- ---- 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH Interrupt control register
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12. ELECTRICAL CHARACTERISTICS
12.1 Absolute Maximum Ratings
(VSS = AVSS = 0 V) Parameter Symbol VCC Power supply voltage AVCC AVR Input voltage Output voltage "L" level max. output current "L" level avg. output current "L" level max. overall output current "L" level avg. overall output current "H" level max. output current "H" level avg. output current "H" level max. overall output current "H" level avg. overall output current Power consumption Operating temperature Storage temperature VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA TSTG Rated Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -- -- -- -- -40 -55 Max. VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 15 4 100 50 -15 -4 -100 -50 300 +85 +150 Units V V V V V mA mA mA mA mA mA mA mA mW C C Average value over a period of 100ms Average value over a period of 100ms Average value over a period of 100ms Average value over a period of 100ms VCC = AVCC AVCC AVR AVss *2 *2 *1 Remarks
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun current to/from a input is limited by some means with external components, the II rating supercedes the VI rating.
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12.2 Recommended Conditions
(VSS = AVSS = 0 V) Parameter Symbol VCC AVCC VIHS Input H voltage VIHM VILS Input L voltage VILM VSS - 0.3 VSS + 0.3 V MD input pin Use a ceramic capacitor or capacitor of better AC characteristics. Capacitor at the VCC should be greater than this capacitor. VCC - 0.3 VSS - 0.3 VCC + 0.3 0.2 VCC V V MD input pin CMOS hysteresis input pin Rated Value Min. 4.5 3.0 0.8 VCC Typ. 5.0 Max. 5.5 5.5 VCC + 0.3 Unit s V V V Remarks Normal operating conditions Maintains RAM data in stop mode. CMOS hysteresis input pin
Power supply voltage
Smooth capacitor
CS
0.022
0.1
1.0
F
Operating temperature
TA
-40
+85
C
C
CS
Figure 12.1 C-Pin Connection Diagram
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13. DC CHARACTERISTICS
(TA = -40 to +85 VCC = 5.0 V 10%, V = AVSS = 0 V) C, SS Parameter Symbol VOH Pin Test Condition VCC = 4.5 V, IOH = -4.0 mA VCC = 4.5 V, IOL = 4.0 mA VCC = 5.5 V, VSS < VI < VCC VCC = 5.0 V10%, Int. frequency: 16 MHz, At normal operating ICC VCC = 5.0 V10%, Int. frequency: 16 MHz, At flash programming VCC = 5.0 V10%, Int. frequency: 16 MHz, At flash erasing ICCS VCC = 5.0 V10%, Int. frequency: 16 MHz, At sleep VCC = 5.0 V 10%, Int. frequency: 16 MHz, At timer mode -- -- Rated Value Min. VCC - 0.5 Typ. -- Max. -- Units Remarks
Output H voltage
All output pins
V
Output L voltage
VOL
All output pins
--
--
0.4
V
Input leak current
IIL
-5
--
5
A mA mA mA MB90497 MB90F497 MB90F497
-- --
35 35 45
40 40 50
45 11 11 0.6 0.6
50 18 18 1.2 1.2
mA mA mA mA mA
MB90F497 MB90497 MB90F497 MB90497 MB90F497
ICTS Power supply current * VCC
ICCL
VCC = 5.0 V, Int. frequency: 8 kHz, At sub operation VCC = 5.0 V, Int. frequency: 8 kHz, At sub sleep VCC = 5.0 V, Int. frequency: 8 kHz, At watch mode VCC = 5.0 V10%, At stop, TA = 25C Other than AVCC, AVSS, AVR, C, VCC, VSS
-- -- -- -- -- -- -- --
16 116 7.5 8 3 3 2 2
20 220 10 20 5 10 20 20
A A A A A A A A pF
MB90497 MB90F497 MB90497 MB90F497 MB90497 MB90F497 MB90497 MB90F497
ICCLS
ICCT
ICCH
Input capacity
CIN
--
--
10
80
*:
Current values are tentative. They are subject to change without notice according to improvements in the characteristics. The power supply current testing conditions are when using the external clock with square pulses.
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14. AC CHARACTERISTICS
14.1 Clock Timing
(TA = -40 to +85 VCC = 5.0 V 10%, V = AVSS = 0 V) C, SS Parameter Symbol fC Oscillation frequency fCL tHCYL Oscillation cycle time tLCYL Frequency deviation with PLL * Input clock pulse width Input clock rise and fall time Machine clock frequency fLCP tCP Machine clock cycle time tLCP -- -- 122.1 -- -- -- -- 62.5 8.192 -- -- 666 kHz ns s When using sub-clock When using main clock When using sub-clock f PWH, PWL PWLH,PWLL tCR, tCF fCP X0A, X1A -- X0 X0A X0 -- -- -- 10 -- -- 1.5 30.5 -- -- 15.2 -- -- -- 5 -- -- 5 16 X0A, X1A X0, X1 -- 62.5 32.768 -- -- 333 kHz ns s % ns s ns MHz Duty ratio is about 30 to 70%. When using external clock When using main clock Pin X0, X1 Rated Value Min. 3 Typ. -- Max. 16 Units MHz Remarks
*: Frequency deviation indicates the maximum frequency difference from the target frequency when using a multiplied clock.
+a
|a| f = x 100% fO
Central frequency fO -a
tHCYL 0.8 VCC X0 0.2 VCC PWH tCF tLCYL 0.8 VCC X0A 0.2 VCC PWLH tCF PWLL tCR PWL tCR
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Guaranteed operation range for MB90F497, MB90497 5.5
4.5 Power supply voltage VCC (V)
Guaranteed PLL operation 3.3 3.0
1.5
3
8 Machine clock fCP (MHz)
12
16
Guaranteed operation range
16
x4
x3
x2
x1
12 Machine clock fCP (MHz) 9 8
x 1/2 (PLL off)
4
3
4
8 Oscillation clock fC (MHz)
16
Ocsillation clock frequency and Machine clock frequency Figure 14.1 Clock Timing
AC characteristics are set to the measured reference voltage values below.
* Input signal waveform
Hysteresis Input Pin 0.8 VCC 0.2 VCC
* Output signal waveform
Output Pin 2.4 V 0.8 V
Figure 14.2 Measured Reference Voltages
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14.2 Clock Output Timing
(TA = -40 to +85 VCC = 5.0 V 10%, V = AVSS = 0.0 V) C, SS Parameter Cycle time CLK CLK Symbol tCYC CLK tCHCL Pin Test Condition Rated Value Min. 62.5 20 Max. -- -- Units ns ns Remarks
VCC = 5 V 10%
tCYC tCHCL 2.4 V CLK 0.8 V 2.4 V
Figure 14.3 Measured CLK timing
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14.3 Reset Input
(TA = -40 to +85 VCC = 5.0 V 10%, V = AVSS = 0.0 V) C, SS Parameter Reset input time Symbol tRSTL Pin RST Rated Value Min. 16 tCP Max. -- Units ns Remarks
"tcp" represents one cycle time of the machine clock. Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.
tRSTL, tHSTL
RST 0.2 VCC 0.2 VCC
Figure 14.4 Measured RST timing
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14.4 Power On Reset
(TA = -40 to +85 VCC = 5.0 V 10%, V = AVSS = 0.0 V) C, SS Parameter Power on rise time Power off time Symbol tR tOFF Pin VCC -- VCC 50 -- ms Due to repetitive operation Test Condition Rated Value Min. 0.05 Max. 30 Units ms Remarks
tR
3.5 V VCC 0.2 V 0.2 V tOFF 0.2 V
If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 mV/sec, you can operate while using the PLL clock.
VCC
3V Holds RAM data VSS
We recommend a rise of 50 mV/ms maximum.
Figure 14.5 Power On Reset Timing
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14.5 External Bus Timing (Read)
(TA = -40 to +85 VCC = 4.5 to 5.5 V, VSS = 0 V) C, Parameter ALE pulse width Valid address ALE time Symbol tLHLL Pin ALE ALE, A23 - A16, AD15 - AD00 ALE, AD15 - AD00 A23 - A16, AD15 - AD00, RD A23 - A16, AD15 - AD00 RD RD, AD15 - AD00 RD, AD15 - AD00 RD, ALE RD, A23 - A16 A23 - A16, AD15 - AD00, CLK RD, CLK ALE, RD -- -- 3 tCP/2 - 60 ns Test Condition Rated Value Min. tCP/2 - 20 Max. Units ns Remarks
tAVLL
tCP/2 - 20
--
ns
ALE Address valid time
tLLAX
tCP/2 - 15
--
ns
Valid address RD time Valid address Valid data input RD pulse width RD Valid data input RD Data hold time RD ALE time RD Address valid time
tAVRL
tCP - 15
--
ns
tAVDV tRLRH tRLDV
-- 3 tCP/2 - 20
5 tCP/2 - 60 --
ns ns
tRHDX tRHLH tRHAX
0 tCP/2 - 15 tCP/2 - 10
-- -- --
ns ns ns
Valid address CLK time RD CLK time ALE RD time
tAVCH
tCP/2 - 20
--
ns
tRLCH tLLRL
tCP/2 - 20 tCP/2 - 15
-- --
ns ns
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MB90495 Series
tAVCH CLK 2.4 V
tRLCH 2.4 V
tAVLL ALE 2.4 V tLHLL tAVRL RD
tLLAX 2.4 V 0.8 V tRLRH 2.4 V 0.8 V tLLRL
tRHLH 2.4 V
tRHAX A23 to A16 2.4 V 0.8 V tRLDV tAVDV AD15 to AD00 2.4 V 0.8 V 2.4 V Address 0.8 V 0.8 VCC 0.2 VCC Read data 2.4 V 0.8 V tRHDX 0.8 VCC 0.2 VCC
Figure 14.6 Bus Timing (Read)
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14.6 External Bus Timing (Write)
(TA = -40 to +85 VCC = 4.5 to 5.5 V, VSS = 0 V) C, Parameter Symbol Pin A23 - A16, AD15 - AD00, WR WR AD15 - AD00, WR -- WR Data hold time WR Address valid time WR ALE time WR CLK time tWHDX tWHAX tWHLH tWLCH AD15 - AD00, WR A23 - A16, WR WR, ALE WR, CLK 20 tCP/2 - 10 tCP/2 - 15 tCP/2 - 20 -- -- -- -- ns ns ns ns Test Condition Rated Value Min. tCP - 15 Max. -- Units Remarks
Valid address WR time WR pulse width Valid data output WR time
tAVWL
ns
tWLWH tDVWH
3 tCP/2 - 20 3 tCP/2 - 20
-- --
ns ns
tWLCH 2.4 V
CLK
tWHLH ALE 2.4 V
tAVWL WR (WRL, WRH) 0.8 V
tWLWH 2.4 V
tWHAX A23 to A16 2.4 V 0.8 V tDVWH AD15 to AD00 2.4 V 0.8 V 2.4 V Address 0.8 V Write data 2.4 V 0.8 V tWHDX 2.4 V 0.8 V
Figure 14.7 Bus Timing (Write)
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14.7 External Bus Ready Input Timing
(TA = -40 to +85 VCC = 4.5 to 5.5 V, VSS = 0 V) C, Parameter RDY setup time RDY hold time Symbol tRYHS tRYHH Pin RDY -- RDY 0 -- ns Test Condition Rated Value Min. 45 Max. -- Units ns Remarks
Note: If the RDY setup time is insufficient, use the auto-ready function.
CLK
2.4 V
ALE
RD/WR
tRYHS RDY no WAIT is used. 0.8 VCC
tRYHH 0.8 VCC
RDY When WAIT is used
0.2 VCC
Figure 14.8 Ready Input Timing
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MB90495 Series
14.8 External Bus Hold Timing
(TA = -40 to +85 VCC = 4.5 to 5.5 V, VSS = 0 V) C, Parameter Pin floating HAK time HAK time Pin valid time Symbol tXHAL tHAHV Pin HAK -- HAK tCP 2 tCP ns Test Condition Rated Value Min. 30 Max. tCP Units ns Remarks
Note: There is more than 1 cycle from when HRQ reads in until the HAK is changed.
HAK 0.8V tXHAL Each pin 2.4V 0.8V High impedance
2.4V
tHAHV 2.4V 0.8V
Figure 14.9 Hold Timing
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14.9 UART1 Timing
(TA = -40 to +85 VCC = 4.5 to 5.5 V, VSS = 0 V) C, Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Notes: 1. AC characteristic in CLK synchronized mode. 2. CL is load capacity value of pins when testing. 3. tCP is the machine cycle (Unit: ns). Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin Symbol SCK1 SCK1, SOT1 SCK1, SIN1 SCK1, SIN1 SCK1 SCK1 SCK1, SOT1 SCK1, SIN1 SCK1, SIN1 External clock operation output pins are CL = 80 pF + 1 TTL. Internal clock operation output pins are CL = 80 pF + 1 TTL. Test Condition Rated Value Min. 8 tCP -80 100 60 4 tCP 4 tCP -- 60 60 Max. -- 80 -- -- -- -- 150 -- -- Units ns ns ns ns ns ns ns ns ns Remarks
tSCYC SCK 2.4 V 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.8 V
Figure 14.10 Internal Shift Clock Mode
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MB90495 Series
tSLSH SCK 0.2 VCC tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC
tSHSL 0.8 VCC
tSHIX 0.8 VCC 0.2 VCC
Figure 14.11 External Shift Clock Mode
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14.10 Timer Related Resource Input Timing
(TA = -40 to +85 VCC = 4.5 to 5.5 V, VSS = 0 V) C, Parameter Symbol tTIWH tTIWL Pin TIN0, TIN1 IN0 to IN3 Test Condition -- Rated Value Min. 4 tCP Max. -- Unit s ns Remarks
Input pulse width
0.8 VCC
0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC
Figure 14.12 Timer Input Timing
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14.11 Timer Related Resource Output Timing
(TA = -40 to +85 VCC = 4.5 to 5.5 V, VSS = 0 V) C, Parameter CLK TOUT change time Symbol Pin TOT0 to TOT1, PPG0 to PPG3 Test Condition Rated Value Min. 30 Max. -- Units Remarks
tTO
--
ns
CLK
2.4 V
TOT/PPG
2.4 V 0.8 V
tTO
Figure 14.13 Timer Output Timing
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MB90495 Series
14.12 External Trigger Input Timing
(TA = -40 to +85 VCC = 4.5 to 5.5 V, VSS = 0 V) C, Parameter Input pulse width Symbol tTRGH tTRGL Pin INT0 to INT7, ADTG Test Condition -- Rated Value Min. 5 tCP Max. -- Units ns Remarks
0.8 VCC
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
Figure 14.14 External Trigger Input Timing
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14.13 A/D Converter
(TA = -40 to +85 3.0 V AVR - AVSS, VCC = AVCC = 5.0 V 10%, V = AVSS = 0 V) C, SS Parameter Resolution Conversion error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Conversion time Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current IAH IR Reference voltage current IRH Offset between input channels -- AVR AN0 to AN7 -- -- -- -- 5 4 AVCC AVR -- 200 -- 400 5 600 Symbol -- -- -- -- VOT VFST -- -- IAIN VAIN -- IA Pin -- -- -- -- AN0 to AN7 AN0 to AN7 -- -- AN0 to AN7 AN0 to AN7 AVR AVCC Rated Value Min. -- -- -- -- AVSS - 3.5 AVR - 6.5 -- -- -- AVSS AVSS + 2.7 -- -- -- -- AVSS +0.5 AVR -1.5 176tCP 64tCP -- -- -- 5 Typ. Max. 10 5.0 2.5 1.9 AVSS + 4.5 AVR + 1.5 -- -- 10 AVR AVCC -- Units bit LSB LSB LSB LSB LSB ns ns A V V mA A A A LSB *1 *1 1 LSB = AVR/1024 Remarks
*1: When not operating A/D converter, this is the current (VCC = AVCC = AVR = 5.0 V) when the CPU is stopped. Terminology: Conversion error : Nonlinearlity : Differential non-linearlity : Zero-reading voltage : Full-scale reading voltage : Notes: 1. The accuracy gets worse as AVR - AVSS becomes smaller. 2. Analog input external circuit output impedance should use the following conditions: External circuit output impedance less than 15 k 3. If the external circuit output impedance is too high, there may be insufficient time for sampling of the analog voltage. Absolute maximum conversion deviation with respect to the theoretical conversion line. Relative maximum conversion deviation with respect to the theoretical conversion line connecting to the device-unique zero reading voltage and full-scale reading voltage. Maximum conversion deviation in any two adjacent reading voltages with respect to the theoretical LSB conversion step. Input voltage which results in the minimum conversion value. Input voltage which results in the maximum coversion value.
Converter C1 Analog input C0
Figure 14.15 Analog Input pin MB90495 Series Data Sheet (Advance Information) 38 / 40
FMG EMDC June 19, 2000
MB90495 Series
15. PACKAGE DIMENSIONS
14.000.20(.551.008)SQ
48
12.000.10(.472.004)SQ
33
1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
49
32
9.75 (.384) REF 1 PIN INDEX
13.00 (.512) NOM
64
17
LEAD No.
1
16
Details of "A" part "A"
M
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
0.127 -0.02 .005 -.001
+0.05 +.002
0.100.10 (STAND OFF) (.004.004)
0.10(.004) 0 10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F64018S-1C-2 Figure 15.1 Package Code: FPT-64P-M09
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MB90495 Series
24.700.40(.972.016)
51
20.000.20(.787.008)
33
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
52
32
14.000.20 (.551.008) INDEX
64 20
18.700.40 (.736.016)
12.00(.472) REF
16.300.40 (.642.016)
"A" LEAD No.
1 19
1.00(.0394) TYP
0.400.10 (.016.004)
0.150.05(.006.002) 0.20(.008)
M
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.00(.709)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX
Details of "B" part
0
10
1.200.20 (.047.008)
C
1994 FUJITSU LIMITED F64013S-3C-2 Figure 15.2 Package Code FPT-64P-M06
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